********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Dec 21, 2015
*ECN S15-2932, Rev. B
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si7454DDP D G S 
M1 3 GX S S NMOS W= 966744u L= 0.30u 
M2 S GX S D PMOS W= 966744u L= 0.45u
R1 D 3 2.18709e-02 6.0404e-03 1.694e-05 
CGS GX S 3.956e-10 
CGD GX D 1.000e-13 
RG G GY 1m 
RTCV 100 S 1e6 1.121e-04 1.174e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 966744u 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.227e-05 NSUB = 1.307e+17 
+ KAPPA = 2.309e-02 theta = 0.07 NFS = 7.860e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.731e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 5.063e-08 TREF = 25 BV = 101 
+RS = 4.682e-03 N = 1.091e+00 IS = 4.841e-12 
+EG = 1.212e+00 XTI = -1.034e+00 TRS = 1.690e-03 
+CJO = 5.432e-10 VJ = 2.000e+01 M = 7.952e-01 ) 
.ENDS 
