*Dec 10, 2012
*ECN S12-2910, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR642DP D G S 
M1 3 GX S S NMOS W= 15114000u L= 0.25u 
M2 S GX S D PMOS W= 15114000u L= 0.19u
R1 D 3 9.518e-04 9.528e-03 2.866e-05 
CGS GX S 1.775e-09 
CGD GX D 8.215e-12 
RG G GY 0.75 
RTCV 100 S 1e6 -1.192e-06 1.474e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 7.504e-04 KP = 9.9473e-06 NSUB = 1.09366e+17 
+ KAPPA = 1.0957e-03 ETA = 1e-4 NFS = 4.508e+11 
+ LD = 0 IS = 0 TPG = 1) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.25e+16 IS = 0 TPG = -1 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 7.342e-09 TREF = 25 BV = 41 
+RS = 1.000e-03 N = 1.004e+00 IS = 4.678e-12 
+EG = 1.185e+00 XTI = 6.932e-01 TRS = 2.005e-03 
+CJO = 4.637e-09 VJ = 2.000e+01 M = 6.140e-01 ) 
.ENDS 
