********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Mar 20, 2017
*ECN S17-0397, Rev. A
*File Name: SiR692DP_PS.txt and SiR692DP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR692DP D G S 
M1 3 GX S S NMOS W= 4431375u L= 0.30u 
M2 S GX S D PMOS W= 4431375u L= 0.45u 
R1 D 3 5.080e-02 TC=9.490e-03,4.028e-05
CGS GX S 1.022e-09 
CGD GX D 1.000e-13 
RG G GY 1m 
RTCV 100 S 1e6 TC=1.002e-05,-1.350e-05
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 4431375u 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 10e-8 
+ RS = 0 KP = 5.431e-06 NSUB = 7.101e+16 
+ KAPPA = 8.970e-03 NFS = 2.930e+11 
+ LD = 0 IS = 0 TPG = 1    )
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 10e-8 
+NSUB = 8.849e+14 IS = 0 TPG = -1    )
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.584e-07 T_measured = 25 BV = 251
+RS = 6.670e-03 N = 1.189e+00 IS = 1.342e-11 
+EG = 1.122e+00 XTI = -7.011e-01 TRS1 = 1.000e-05
+CJO = 7.864e-10 VJ = 2.565e+00 M = 9.990e-01 ) 
.ENDS 
