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* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Mar 20, 2017
*ECN S17-0400, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR632DP D G S 
M1 3 GX S S NMOS W= 2281590u L= 0.30u 
M2 S GX S D PMOS W= 2281590u L= 0.28u 
R1 D 3 2.381e-02 8.251e-03 3.318e-05 
CGS GX S 5.833e-10 
CGD GX D 1.000e-13 
RG G GY 1m 
RTCV 100 S 1e6 9.773e-04 4.168e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 2281590u 
*************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 10e-8 
+ RS = 0 KP = 3.021e-06 NSUB = 5.879e+16 
+ KAPPA = 2.005e-02 NFS = 1.166e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 10e-8 
+NSUB = 8.055e+15 IS = 0 TPG = -1 CAPOP = 12 ) 
***************************************************  
.MODEL DBD D ( 
+FC = 0.1 TT = 1.572e-07 TREF = 25 BV = 151 
+RS = 5.402e-03 N = 1.177e+00 IS = 1.306e-11 
+EG = 1.234e+00 XTI = -1.084e+00 TRS = 2.132e-03 
+CJO = 7.784e-10 VJ = 6.134e+00 M = 9.419e-01 ) 
.ENDS 
