********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Dec 28, 2015
*ECN S15-3027, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT  SiRC04DP D G S 
X1 D G S SiRC04DP_nm 
X2 S D   SiRC04DP_schottky 
.ENDS SiRC04DP 
.SUBCKT SiRC04DP_nm D G S 
M1 3 GX S S NMOS W= 6350000u L= 0.30u 
M2 S GX S D PMOS W= 6350000u L= 0.13u
R1 D 3 1.769e-03 3.890e-03 1.102e-05 
CGS GX S 1.743e-09 
CGD GX D 1.000e-12 
RG G GY 1m 
RTCV 100 S 1e6 6.373e-04 -5.013e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.821e-05 NSUB = 9.703e+16 
+ KAPPA = 9.076e-02 NFS = 3.430e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.161e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
**************************************************************** 
.ENDS SiRC04DP_nm
.subckt SiRC04DP_schottky 7 5 
d1 7 5 sdsm 
d2 7 5 sdlg 
d3 7 4 sdrev 
d4 5 4 sdblk 
.MODEL sdsm d (IS = 1.222e-12 N = 9.778e-01 EG = 1.150e+00 
+XTI = 6.390e-01 RS = 1.137e-03 TRS = 3.405e-03 ) 
.MODEL sdlg d (IS = 9.910e-06 N = 1.072e+00 EG = 5.975e-01 
+XTI = 3.233e-01 RS = 2.000e-02 TRS = 3.578e-03 
+VJ = 5.000e+00 CJO = 4.467e-09 M = 1.104e+00 
+TT = 4.564e-08 ) 
.MODEL sdrev d (IS = 6.19e-06 N = 1.395e+00 EG = 5.177e-01 
+XTI = 1.079e+01 ) 
.MODEL sdblk d (IS = 1e-11 N=1) 
.ends SiRC04DP_schottky 
