********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Jan 23, 2017
*ECN S17-0110, Rev. A
*File Name: SiRA96DP_PS.txt and SiRA96DP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiRA96DP D G S 
M1 3 GX S S NMOS W= 2817500u L= 0.30u 
M2 S GX S D PMOS W= 2817500u L= 0.24u 
R1 D 3 6.401e-03 TC=3.053e-03,8.391e-06
CGS GX S 8.954e-10 
CGD GX D 1.000e-13 
RG G GY 1m 
RTCV 100 S 1e6 TC=5.977e-04,-2.263e-06
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 2817500u 
******************************************************  
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.290e-05 NSUB = 7.336e+16 
+ KAPPA = 4.195e-02 NFS = 1.070e+11 
+ LD = 0 IS = 0 TPG = 1    )
****************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 7.197e+15 IS = 0 TPG = -1    )
******************************************************  
.MODEL DBD D ( 
+FC = 0.1 TT = 1.600e-07 T_measured = 25 BV = 31
+RS = 1.469e-02 N = 1.137e+00 IS = 1.664e-11 
+EG = 1.063e+00 XTI = 2.980e+00 TRS1 = 8.251e-04
+CJO = 5.620e-10 VJ = 5.816e+00 M = 9.990e-01 ) 
.ENDS 
