********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Jan 23, 2017
*ECN S17-0118, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR668DP D G S 
M1 3 GX S S NMOS W= 12962500u L= .3u
 
M2 S GX S D PMOS W= 12962500u L= 0.2u 
R1 D 3 3.485e-03 8.280e-03 3.017e-05 
CGS GX S 3.632e-09 
CGD GX D 1.008e-13 
RG G GY 1m 
RTCV 100 S 1e6 -4.473e-04 -1.064e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 12962500u 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 7e-8 
+ RS = 0 KP = 7.305e-06 NSUB = 1.252e+17 
+ KAPPA = 7.713e-02 NFS = 3.050e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 7e-8 
+NSUB = 1.493e+15 IS = 0 TPG = -1 CAPOP = 12 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 2.000e-07 TREF = 25 BV = 101
 
+RS = 9.729e-03 N = 1.114e+00 IS = 2.533e-12 
+EG = 1.214e+00 XTI = 1.178e-01 TRS = 2.708e-03 
+CJO = 4.911e-10 VJ = 1.753e+00 M = 9.362e-01 ) 
.ENDS 
