********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Jun 19, 2017
*ECN S17-0932, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si4848ADY D G S 
M1 3 GX S S NMOS W= 990810u L= 0.30u 
M2 S GX S D PMOS W= 990810u L= 0.30u 
R1 D 3 4.924e-02 9.699e-03 2.776e-06 
CGS GX S 3.077e-10 
CGD GX D 1.000e-13 
RG G GY 1m 
RTCV 100 S 1e6 6.927e-03 3.322e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 990810u 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 10e-8 
+ RS = 0 KP = 2.929e-06 NSUB = 6.881e+16 
+ KAPPA = 2.001e-02 NFS = 5.805e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 10e-8 
+NSUB = 4.021e+15 IS = 0 TPG = -1 CAPOP = 12 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.000e-07 TREF = 25 BV = 151 
+RS = 7.485e-03 N = 1.117e+00 IS = 4.810e-12 
+EG = 1.241e+00 XTI = 3.023e-01 TRS = 3.342e-03 
+CJO = 8.203e-10 VJ = 6.926e+00 M = 1.000e+00 ) 
.ENDS 
