********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Jan 23, 2017
*ECN S17-0120, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR624DP D G S 
M1 3 GX S S NMOS W= 2386125u L= 0.30u 
M2 S GX S D PMOS W= 2386125u L= 0.29u 
R1 D 3 4.710e-02 8.062e-03 2.852e-05 
CGS GX S 7.936e-10 
CGD GX D 1.000e-13 
RG G GY 1m 
RTCV 100 S 1e6 1.894e-04 -1.775e-05 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 2386125u 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 7e-8 
+ RS = 0 KP = 4.810e-06 NSUB = 1.348e+17 
+ KAPPA = 1.704e-02 NFS = 5.000e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 7e-8 
+NSUB = 9.985e+15 IS = 0 TPG = -1 CAPOP = 12 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 2.000e-07 TREF = 25 BV = 201 
+RS = 5.616e-03 N = 1.169e+00 IS = 8.616e-12 
+EG = 1.220e+00 XTI = -4.452e-01 TRS = 1.910e-03 
+CJO = 8.498e-10 VJ = 4.788e+00 M = 1.000e+00 ) 
.ENDS 
