********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Jun 19, 2017
*ECN S17-0926, Rev. B
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiSS64DN D G S 
M1 3 GX S S NMOS W= 8250000u L= 0.30u 
M2 S GX S D PMOS W= 8250000u L= 0.14u 
R1 D 3 1.493e-03 3.631e-03 1.378e-05 
CGS GX S 1.890e-09 
CGD GX D 1.008e-13 
RG G GY 1m 
RTCV 100 S 1e6 0.147e-03 0.576e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 8250000u 
**************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 2.171e-05 NSUB = 9.539e+16 
+ KAPPA = 1.000e+00 NFS = 2.430e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
****************************************************  
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 8.590e+15 IS = 0 TPG = -1 CAPOP = 12 ) 
****************************************************  
.MODEL DBD D ( 
+FC = 0.1 TT = 9.473e-09 TREF = 25 BV = 31 
+RS = 7.544e-03 N = 1.158e+00 IS = 2.577e-11 
+EG = 1.184e+00 XTI = -3.223e-01 TRS = 2.574e-03 
+CJO = 6.206e-10 VJ = 3.888e+00 M = 9.990e-01 ) 
.ENDS 
