Industry-best Performance In Advanced Thermal Packaging for Power MOSFETs

PowerPAK SO-8 PowerPAK 1212-8
INCREASE EFFICIENCY
• On-resistance as low as 2 mΩ
• On-resistance x gate-charge product as low as 115 		• On-resistance as low as 11 mΩ
INCREASE POWER WITHOUT INCREASING FOOTPRINT, HEIGHT, OR HEAT
• Maximum power possible in the SO-8 increases from 3 W to 5 W • Maximum power possible in the TSSOP-8 increases from 2.4 W to 3.5 W
REDUCE AREA AND HEIGHT FOR ULTRA-THIN AND LIGHTWEIGHT APPLICATIONS
• 53% smaller footprint area and 55% thinner than the DPAK
• 39% thinner than the SO-8 		• 48% smaller footprint area and 11% thinner than the TSSOP-8
REDUCE HEAT WITH LOWER THERMAL RESISTANCE IN A SIMILAR PACKAGE SIZE
• Pin-compatible to SO-8, with similar footprint size and decrease in thermal resistance from 16°C/W to <1°/W
• Same thermal resistance as DPAK 		• Thermal resistance decrease from 34°C/W to <2°C/W in the TSSOP-8 with smaller footprint and thinner profile

• PowerPAKŪ SO-8 selector guide
• PowerPAKŪ 1212-8 selector guide

More About PowerPAK Power MOSFETs

Siliconix PowerPAK Power MOSFET family’s industry low on-resistance breaks the 3 mΩ barrier for 20 V and 30 V devices in an SO-8 footprint. These PWM-optimized devices feature on-resistance-times-gate-charge products as low as 115.

The PowerPAK’s innovative leadless packaging provides a direct thermal path between the power MOSFET die and the natural heat sink supplied by the printed circuit board. The thermal path is established by soldering the die-attach copper pad directly to the PCB. This leadless technology also provides for ultra-thin package profiles.

PACKAGE COMPARISON

  DPAK PowerPAK SO-8 SO-8 PowerPAK 1212-8 TSSOP-8
Rthjc or Rthjf 1.2°C/W < 1°C/W < 16°C/W < 2°C/W 34°C/W
Footprint Area 70.06 mm2 31.5 mm2 31.0 mm2 10.9 mm2 20.5 mm
Profile 2.39 mm 1.07 mm 1.75 mm 1.05 mm 1.2 mm
1 Typical for single channel

PowerPAKŪ single (bottom)
Backside view of single pad

PowerPAKŪ dual (bottom)

 ** PowerPAK 1212-8
*** PowerPAK SO-8

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