*May 06, 2013
*ECN S13-0942, Rev. B
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR800DP D G S 
M1 3 GX S S NMOS W= 8515787u L= 0.25u 
M2 S GX S D PMOS W= 8515787u L= 1.972e-07 
R1 D 3 9.884e-04 6.496e-03 1.122e-05 
CGS GX S 3.280e-09 
CGD GX D 2.156e-10 
RG G GY 1.2 
RTCV 100 S 1e6 9.790e-05 -3.112e-07 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 3e-8 
+ RS = 6.876e-04 KP = 2.223e-05 NSUB = 9.95e+16 
+ KAPPA = 1.000e-06 ETA = 3.102e-06 NFS = 5.841e+11 
+ LD = 0 IS = 0 TPG = 1) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 3e-8 
+NSUB = 3.732e+16 IS = 0 TPG = -1 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.046e-08 TREF = 25 BV = 22 
+RS = 2.237e-03 N = 1.075e+00 IS = 6.285e-10 
+EG = 8.305e-01 XTI = 4.963e+00 TRS = 1.000e-05 
+CJO = 1.950e-09 VJ = 6.902e-01 M = 3.423e-01 ) 
.ENDS 
