********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Sep 04, 2017
*ECN S17-1381, Rev. A
*File Name: SiR186DP_PS.txt and SiR186DP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR186DP D G S 
M1 3 GX S S NMOS W= 4265000u L= 0.30u 
M2 S GX S D PMOS W= 4265000u L= 0.24u 
R1 D 3 2.301e-03 TC=5.919e-03,3.308e-05
CGS GX S 1.120e-09 
CGD GX D 1.000e-13 
RG G GY 1m 
RTCV 100 S 1e6 TC=1.089e-03,-1.056e-06
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 4265000u 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 7e-8 
+ RS = 0 KP = 6.768e-06 NSUB = 1.129e+17 
+ KAPPA = 1.895e-02 NFS = 3.400e+11 
+ LD = 0 IS = 0 TPG = 1    )
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 7e-8 
+NSUB = 5.509e+15 IS = 0 TPG = -1    )
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.201e-07 T_measured = 25 BV = 60.5
+RS = 4.727e-03 N = 1.125e+00 IS = 3.275e-12 
+EG = 1.215e+00 XTI = -1.377e-01 TRS1 = 2.082e-03
+CJO = 4.149e-10 VJ = 1.014e+01 M = 1.000e+00 ) 
.ENDS 
