********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Apr 09, 2018
*ECN S18-0410, Rev. A
*File Name: SiSH402DN_PS.txt and SiSH402DN_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiSH402DN D G S
M1  3  GX S S NMOS W=3586577u L=0.25u       
M2  S  GX S D PMOS W=3586577u L=0.25u 
RG  G  GX     1.2
R1  D  3      RTEMP 1.9E-3
CGS GX S      960E-12
DBD S  D      DBD
************************************************************ 
.MODEL  NMOS       NMOS ( LEVEL  = 3         TOX    = 5E-8
+ RS     = 2.04E-3        RD     = 0         NSUB   = 2.6E17  
+ KP     = 1.55E-5        UO     = 650             
+ VMAX   = 0              XJ     = 5E-7      KAPPA  = 5E-2
+ ETA    = 1E-4           TPG    = 1  
+ IS     = 0              LD     = 0            
+ CGSO   = 0              CGDO   = 0         CGBO   = 0 
+ NFS    = 0.8E12         DELTA  = 0.1)
************************************************************ 
.MODEL  PMOS       PMOS ( LEVEL  = 3         TOX    = 5E-8
+NSUB    = 3.4E16         IS     = 0         TPG    = -1)   
************************************************************  
.MODEL DBD D (CJO=820E-12 VJ=0.38 M=0.32
+FC=0.5 TT=1.36e-08 T_MEASURED=25 BV=31 
+RS=1.248e-03 N=1.19 IS=8.886e-11 IKF=1000
+EG=1.183 XTI=8.398e-01 TRS1=2.353e-03 )
************************************************************ 
.MODEL RTEMP RES (TC1=9E-3 TC2=5.5E-6)
************************************************************ 
.ENDS
