********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Dec 25, 2017
*ECN S17-1889, Rev. A
*File Name: SiR180DP_PS.txt and SiR180DP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR180DP D G S 
M1 3 GX S S NMOS W= 10787500u L= 0.30u 
M2 S GX S D PMOS W= 10787500u L= 0.16u 
R1 D 3 1.200e-03 TC=9.214e-03,5.570e-05
CGS GX S 2.709e-09 
CGD GX D 1.008e-13 
RG G GY 0.90 
RTCV 100 S 1e6 TC=1.021e-04,0.512e-05
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 10787500u 
************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 7e-8 
+ RS = 0 KP = 8.558e-06 NSUB = 1.122e+17 
+ KAPPA = 1.045e-01 NFS = 1.003e+11 
+ LD = 0 IS = 0 TPG = 1    )
************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 7e-8 
+NSUB = 6.910e+15 IS = 0 TPG = -1    )
************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.117e-07 T_measured = 25 BV = 61
+RS = 7.298e-03 N = 1.042e+00 IS = 1.030e-12 
+EG = 1.217e+00 XTI = -1.554e-01 TRS1 = 5.364e-03
+CJO = 3.747e-10 VJ = 1.086e+01 M = 9.990e-01 ) 
.ENDS 
