********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Apr 23, 2018
*ECN S18-0467, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiRA80DP D G S 
M1 3 GX S S NMOS W= 23850000u L= 0.30u 
M2 S GX S D PMOS W= 23850000u L= 0.21u 
R1 D 3 3.4731e-04 2.598e-03 1.006e-05 
CGS GX S 4.898e-09 
CGD GX D 1.000e-13 
RG G GY 0.4 
RTCV 100 S 1e6 1.026e-04 1.010e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 23850000u 
************************************************ 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.344e-05 NSUB = 8.110e+16 
+ KAPPA = 5.060e-03 NFS = 1.056e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
************************************************ 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.442e+15 IS = 0 TPG = -1 CAPOP = 12 ) 
************************************************ 
.MODEL DBD D ( 
+FC = 0.1 TT = 9.438e-08 TREF = 25 BV = 31 
+RS = 1.104e-02 N = 9.507e-01 IS = 1.000e-13 
+EG = 1.140e+00 XTI = 2.759e+00 TRS = 3.299e-03 
+CJO = 5.232e-10 VJ = 4.819e+00 M = 9.990e-01 ) 
.ENDS 
