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* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*12-Nov-2018
*ECN S18-1142, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SUP50010E D G S 
M1 3 GX S S NMOS W= 27337500u L= 0.30u 
M2 S GX S D PMOS W= 27337500u L= 0.10u 
R1 D 3 1.050e-03 4.758e-03 1.000e-05 
CGS GX S 7.521e-09 
CGD GX D 1.008e-13 
RG G GY 1.2 
RTCV 100 S 1e6 1.2069e-03 -.072e-04 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 27337500u 
************************************************* 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 7e-8 
+ RS = 0 KP = 2.590e-06 NSUB = 1.240e+17 
+ KAPPA = 1.100e-01 NFS = 1.009e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
************************************************* 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 7e-8 
+NSUB = 9.943e+15 IS = 0 TPG = -1 CAPOP = 12 ) 
************************************************* 
.MODEL DBD D ( 
+FC = 0.1 TT = 5e-8 TREF = 25 BV = 61 
+RS = 3.637e-02 N = 1.105e+00 IS = 2.496e-12 
+EG = 1.213e+00 XTI = 5.011e-01 TRS = 4.233e-03 
+CJO = 3.861e-10 VJ = 5.898e+00 M = 7.924e-01 ) 
.ENDS 
