********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*06-May-2019
*ECN S19-0412, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.                 	

.SUBCKT SiSS30LDN D G S 

M1 3 GX S S NMOS W= 4262500U L= 3E-7 

M2 S GX S D PMOS W= 4262500U L= 1.85E-7

R1 D 3 5.1096E-3 9.2E-3 3.174E-5 

CGS GX S 1.85E-9
CGD GX D 3.331E-12 
RG G GY 0.81
RTCV 100 S 1E6 1.027E-3 -7.3E-6
ETCV GX GY 100 200 1
ITCV S 100 1U
VTCV 200 S 1
DBD S D DBD 4262500U

**************************************************************** 

.MODEL NMOS NMOS
+ LEVEL = 3                     	 TOX = 5E-8                    	 RS = 7.1E-4                   	
+ KP = 7.35E-6                  	 NSUB = 9.28E16                	 KAPPA = 0.041                 	
+ NFS = 2.1E11                  	 LD = 0                        	 IS = 0                        	
+ TPG = 1                       	 CAPOP = 12                    	 ETA = 5E-6
****************************************************************                    	
.MODEL PMOS PMOS
+ LEVEL = 3                     	 TOX = 7E-8                    	 NSUB = 6.2E15                 	
+ IS = 0                        	 TPG = -1                      	 CAPOP = 12        
****************************************************************            	
.MODEL DBD D
+ FC = 0.1                      	 TT = 4.778E-8                 	 TREF = 25                     	
+ BV = 81                       	 RS = 6.2E-3                   	 N = 1.083542                  	
+ IS = 2.9E-12                  	 EG = 1.2                      	 XTI = -0.348                  	
+ TRS = 3.533E-4                	 CJO = 4.05E-10                	 VJ = 1.73                     	
+ M = 0.71                      	

****************************************************************
.ENDS
