********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*25-Jun-2018
*ECN S18-0629, Rev. A
*File Name: SiR668ADP_PS.txt and SiR668ADP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR668ADP  D G S 
M1 3 GX S S NMOS W= 12962500u L= 0.30u 
M2 S GX S D PMOS W= 12962500u L= 0.28u 
R1 D 3 2.408e-03 TC=9.993e-03,4.710e-05
CGS GX S 2.587e-09 
CGD GX D 1.640e-12 
RG G GY 0.99 
RTCV 100 S 1e6 TC=1.776e-03,-0.575e-05
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 12962500u 
************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 10e-8 
+ RS = 0 KP = 2.238e-06 NSUB = 7.885e+16 
+ KAPPA = 9.066e-02 NFS = 5.360e+11 
+ LD = 0 IS = 0 TPG = 1    )
************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 10e-8 
+NSUB = 1.994e+14 IS = 0 TPG = -1    )
************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 2.000e-07 T_measured = 25 BV = 101
+RS = 1.055e-02 N = 1.023e+00 IS = 6.088e-13 
+EG = 1.337e+00 XTI = -5.158e+00 TRS1 = 2.616e-03
+CJO = 4.910e-10 VJ = 1.819e+00 M = 8.269e-01 ) 
.ENDS 
