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* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*06-Aug-2018
*ECN S18-0786, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiSS65DN D G S 
M1 3 GX S S PMOS W= 10200000u L= 0.30u 
M2 S GX S D NMOS W= 10200000u L= 0.23u 
R1 D 3 2.807e-03 3.843e-03 4.487e-06 
CGS GX S 3.190e-09 
CGD GX D 2.821e-10 
RG G GY 1.6 
RTCV 100 S 1e6 0.107e-03 0.346e-05 
ETCV GY GX 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD D S DBD 10200000u 
************************************************* 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 3.388e-06 NSUB = 2.276e+16 
+ KAPPA = 1.044e-02 NFS = 2.121e+11 
+ LD = 0 IS = 0 TPG = -1 CAPOP = 12 ) 
************************************************* 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 2.701e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
************************************************* 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.104e-07 TREF = 25 BV = 31 
+RS = 1.376e-02 N = 1.071e+00 IS = 2.922e-12 
+EG = 1.231e+00 XTI = -3.350e+00 TRS = 7.985e-04 
+CJO = 2.000e-11 VJ = 3.342e+00 M = 7.037e-01 ) 
.ENDS 
