********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*24-Sep-2018
*ECN S18-0976, Rev. A
*File Name: SiRA50ADP_PS.txt and SiRA50ADP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiRA50ADP D G S 
M1 3 GX S S NMOS W= 17360000u L= 0.30u 
M2 S GX S D PMOS W= 17360000u L= 0.06u 
R1 D 3 7.292e-04 TC=3.597e-03,9.163e-06
CGS GX S 4.723e-09 
CGD GX D 1.000e-13 
RG G GY 0.7 
RTCV 100 S 1e6 TC=1.070e-04,1.955e-06
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 17360000u 
************************************************* 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.361e-05 NSUB = 1.148e+17 
+ KAPPA = 2.087e-01 NFS = 3.045e+11 
+ LD = 0 IS = 0 TPG = 1    )
************************************************* 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 5.059e+16 IS = 0 TPG = -1    )
************************************************* 
.MODEL DBD D ( 
+FC = 0.1 TT = 7.518e-08 T_measured = 25 BV = 41
+RS = 5.145e-02 N = 1.062e+00 IS = 1.560e-12 
+EG = 8.366e-01 XTI = 9.094e+00 TRS1 = 1.000e-05
+CJO = 3.328e-10 VJ = 7.068e+00 M = 9.990e-01 ) 
.ENDS 
