********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*01-Oct-2018
*ECN S18-0990, Rev. A
*File Name: SiR124DP_PS.txt and SiR124DP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR124DP D G S 
M1 3 GX S S NMOS W= 4262500u L= 0.30u 
M2 S GX S D PMOS W= 4262500u L= 0.17u 
R1 D 3 4.560e-03 TC=8.204e-03,4.074e-05
CGS GX S 1.322e-09 
CGD GX D 1.391e-12 
RG G GY 0.81 
RTCV 100 S 1e6 TC=1.027e-03,-0.730e-05
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 4262500u 
*************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 7e-8 
+ RS = 0 KP = 4.406e-06 NSUB = 1.114e+17 
+ KAPPA = 1.388e-01 NFS = 1.006e+11 
+ LD = 0 IS = 0 TPG = 1    )
*************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 7e-8 
+NSUB = 5.303e+15 IS = 0 TPG = -1    )
*************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 4.778e-08 T_measured = 25 BV = 81
+RS = 7.689e-03 N = 9.714e-01 IS = 1.000e-13 
+EG = 1.188e+00 XTI = -3.480e-01 TRS1 = 3.533e-04
+CJO = 5.392e-10 VJ = 1.439e+00 M = 7.943e-01 ) 
.ENDS 
