********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*01-Oct-2018
*ECN S18-1001, Rev. A
*File Name: SiSS32DN_PS.txt and SiSS32DN_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiSS32DN D G S 
M1 3 GX S S NMOS W= 3002365u L= 0.30u 
M2 S GX S D PMOS W= 3002365u L= 0.25u 
R1 D 3 4.480e-03 TC=7.521e-03,2.999e-05
CGS GX S 1.724e-09 
CGD GX D 1.000e-13 
RG G GY 0.83 
RTCV 100 S 1e6 TC=1.003e-04,1.876e-06
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 3002365u 
***************************************************  
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 7e-8 
+ RS = 0 KP = 1.047e-05 NSUB = 1.342e+17 
+ KAPPA = 3.773e-01 NFS = 3.687e+11 
+ LD = 0 IS = 0 TPG = 1    )
***************************************************  
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 7e-8 
+NSUB = 5.931e+15 IS = 0 TPG = -1    )
***************************************************  
.MODEL DBD D ( 
+FC = 0.1 TT = 7.154e-08 T_measured = 25 BV = 81
+RS = 3.245e-03 N = 1.092e+00 IS = 4.051e-12 
+EG = 1.207e+00 XTI = -1.190e-01 TRS1 = 2.345e-03
+CJO = 4.057e-10 VJ = 9.783e+00 M = 1.000e+00 ) 
.ENDS 
