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* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*16-Jul-2018
*ECN S18-0724, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiRA52ADP D G S 
M1 3 GX S S NMOS W= 13134000u L= 0.30u 
M2 S GX S D PMOS W= 13134000u L= 0.08u 
R1 D 3 1.100e-03 3.692e-03 1.123e-05 
CGS GX S 3.004e-09 
CGD GX D 1.008e-13 
RG G GY 1.1 
RTCV 100 S 1e6 1.012e-05 1.415e-07 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 13134000u 
************************************************* 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.415e-05 NSUB = 1.371e+17 
+ KAPPA = 4.477e-01 NFS = 7.050e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
************************************************* 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 2.838e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
************************************************* 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.958e-07 TREF = 25 BV = 41 
+RS = 1.619e-02 N = 1.044e+00 IS = 2.267e-12 
+EG = 1.147e+00 XTI = 7.810e-02 TRS = 2.885e-04 
+CJO = 2.665e-10 VJ = 6.116e+00 M = 9.990e-01 ) 
.ENDS 
