********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Dec 18, 2017
*ECN S17-1847, Rev. A
*File Name: SiR182DP_PS.txt and SiR182DP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR182DP D G S 
M1 3 GX S S NMOS W= 7970000u L= 0.30u 
M2 S GX S D PMOS W= 7970000u L= 0.11u 
R1 D 3 1.610e-03 TC=5.135e-03,1.279e-05
CGS GX S 2.264e-09 
CGD GX D 1.008e-13 
RG G GY 0.76m  
RTCV 100 S 1e6 TC=2.207e-03,9.815e-06
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 7970000u 
************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 7e-8 
+ RS = 0 KP = 8.227e-06 NSUB = 1.158e+17 
+ KAPPA = 1.187e-03 NFS = 1.083e+11 
+ LD = 0 IS = 0 TPG = 1    )
************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 7e-8 
+NSUB = 2.418e+16 IS = 0 TPG = -1    )
************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 2.000e-07 T_measured = 25 BV = 61
+RS = 8.518e-03 N = 1.112e+00 IS = 2.318e-12 
+EG = 1.173e+00 XTI = 5.204e-01 TRS1 = 1.569e-03
+CJO = 4.749e-10 VJ = 8.579e+00 M = 9.990e-01 ) 
.ENDS 
