********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Dec 25, 2017
*ECN S17-1911, Rev. A
*File Name: SiR164ADP_PS.txt and SiR164ADP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR164ADP D G S 
M1 3 GX S S NMOS W= 7312500u L= 0.25u 
M2 S GX S D PMOS W= 7312500u L= 1.355e-07 
R1 D 3 1.5499e-03 TC=2.618e-03,1.103e-05 
CGS GX S 2.468e-09 
CGD GX D 1.000e-13 
RG G GY 1.25 
RTCV 100 S 1e6 TC=4.951e-04,3.798e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 7312500u 
************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.4287e-05 NSUB = 1.02e+17
+ KAPPA = 1.000e-06 NFS = 4.069e+11 
+ LD = 0 IS = 0 TPG = 1   ) 
************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.304e+16 IS = 0 TPG = -1  ) 
************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 2.000e-08 T_MEASURED = 25 BV = 31 
+RS = 2.781e-02 N = 9.892e-01 IS = 5.114e-13 
+EG = 1.153e+00 XTI = -5.905e-02 TRS1 = 1.000e-05 
+CJO = 4.863e-10 VJ = 5.925e+00 M = 1.000e-00 ) 
.ENDS 
