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* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Oct 23, 2017
*ECN S17-1635, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiRA01DP D G S 
M1 3 GX S S PMOS W= 7312500u L= 0.30u 
M2 S GX S D NMOS W= 7312500u L= 0.28u 
R1 D 3 3.230e-03 2.588e-03 2.064e-06 
CGS GX S 1.997e-09 
CGD GX D 1.008e-13 
RG G GY 3.5
RTCV 100 S 1e6 1.425e-03 1.570e-06 
ETCV GY GX 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD D S DBD 7312500u 
************************************************* 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 5.256e-06 NSUB = 3.224e+16 
+ KAPPA = 5.034e-03 NFS = 4.992e+11 
+ LD = 0 IS = 0 TPG = -1 CAPOP = 12 ) 
************************************************* 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.184e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
*************************************************  
.MODEL DBD D ( 
+FC = 0.1 TT = 1.001e-07 TREF = 25 BV = 30.6 
+RS = 1.440e-02 N = 1.079e+00 IS = 4.117e-12 
+EG = 1.176e+00 XTI = -1.301e+00 TRS = 6.060e-04 
+CJO = 4.399e-10 VJ = 1.048e+01 M = 1.000e+00 ) 
.ENDS 
