********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Feb 01, 2016
*ECN S16-0111, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits
.SUBCKT SiRC06DP D G S 
X1 D G S SiRC06DP_nm 
X2 S D SiRC06DP_schottky 
.ENDS SiRC06DP 
.SUBCKT SiRC06DP_nm D G S 
M1 3 GX S S NMOS W= 5790000u L= 0.30u 
M2 S GX S D PMOS W= 5790000u L= 0.14u 
R1 D 3 1.741e-03 3.534e-03 1.2551e-05 
CGS GX S 1.634e-09 
CGD GX D 1.001e-12 
RG G GY 1m 
RTCV 100 S 1e6 2.872e-04 -3.857e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
********************************************************  
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.654e-05 NSUB = 7.423e+16 
+ KAPPA = 1.029e-01 NFS = 6.480e+10 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
******************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.184e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
******************************************************** 
.ENDS SiRC06DP_nm
.subckt SiRC06DP_schottky 7 5 
d1 7 5 sdsm 
d2 7 5 sdlg 
d3 7 4 sdrev 
d4 5 4 sdblk 
.MODEL sdsm d (IS = 1.389e-11 N = 1.059e+00 EG = 1.091e+00 
+XTI = 3.365e+00 RS = 1.393e-03 TRS = 2.910e-03 ) 
.MODEL sdlg d (IS = 9.166e-06 N = 1.097e+00 EG = 6.246e-01 
+XTI = 3.245e-02 RS = 2.000e-02 TRS = 5.283e-03 
+VJ = 5.000e+00 CJO = 3.900e-09 M = 1.070e+00 
+TT = 3.480e-08 ) 
.MODEL sdrev d (IS = 6.934e-06 N = 1.399e+00 EG = 5.000e-01 
+XTI = 1.101e+01 ) 
.MODEL sdblk d (IS = 1e-11 N=1) 
.ends SiRC06DP_schottky 
