********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*29-Oct-2018
*ECN S18-1099, Rev. A
*File Name: SiR608DP_PS.txt and SiR608DP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR608DP D G S 
M1 3 GX S S NMOS W= 19640000u L= 0.30u 
M2 S GX S D PMOS W= 19640000u L= 0.07u 
R1 D 3 8.638e-04 TC=4.935e-03,1.306e-07
CGS GX S 5.788e-09 
CGD GX D 1.008e-13 
RG G GY 0.88  
RTCV 100 S 1e6 TC=1.006e-04,-5.959e-06
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 19640000u 
************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.501e-05 NSUB = 1.206e+17 
+ KAPPA = 1.333e-02 NFS = 3.082e+11 
+ LD = 0 IS = 0 TPG = 1    )
**************************************************  
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.324e+16 IS = 0 TPG = -1    )
************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 7.511e-08 T_measured = 25 BV = 46
+RS = 4.098e-03 N = 1.106e+00 IS = 1.000e-13 
+EG = 1.316e+00 XTI = 8.126e+00 TRS1 = 2.138e-02
+CJO = 3.103e-10 VJ = 5.538e+00 M = 9.990e-01 ) 
.ENDS 
