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* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*01-Oct-2018
*ECN S18-1004, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR826BDP D G S 
M1 3 GX S S NMOS W= 7971250u L= 0.30u 
M2 S GX S D PMOS W= 7971250u L= 0.18u 
R1 D 3 3.672e-03 7.148e-03 3.444e-05 
CGS GX S 2.403e-09 
CGD GX D 9.972e-13 
RG G GY 0.75 
RTCV 100 S 1e6 -2.451e-04 -5.666e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 7971250u 
*************************************************  
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 7e-8 
+ RS = 0 KP = 1.346e-05 NSUB = 1.414e+17 
+ KAPPA = 1.452e-01 NFS = 2.406e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*************************************************  
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 7e-8 
+NSUB = 4.005e+15 IS = 0 TPG = -1 CAPOP = 12 ) 
*************************************************  
.MODEL DBD D ( 
+FC = 0.1 TT = 2.000e-08 TREF = 25 BV = 81 
+RS = 1.073e-02 N = 1.003e+00 IS = 1.173e-13 
+EG = 8.431e-01 XTI = 1.000e+01 TRS = 1.010e-05 
+CJO = 5.554e-10 VJ = 3.939e+00 M = 9.990e-01 ) 
.ENDS 
