********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Sep 11, 2017
*ECN S17-1419, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.

.SUBCKT SiDR680DP D G S 
M1 3 GX S S NMOS W= 12962500u L= 0.30u
 
M2 S GX S D PMOS W= 12962500u L= 0.20u 
R1 D 3 2.094e-03 8.090e-03 3.623e-05 
CGS GX S 3.316e-09 
CGD GX D 1.008e-13 
RG G GY 1m 
RTCV 100 S 1e6 1.074e-04 -4.119e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 12962500u 
************************************************ 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 7e-8 
+ RS = 0 KP = 1.204e-05 NSUB = 1.390e+17 
+ KAPPA = 3.328e-03 NFS = 4.050e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
************************************************  
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 7e-8 
+NSUB = 2.518e+15 IS = 0 TPG = -1 CAPOP = 12 ) 
************************************************  
.MODEL DBD D ( 
+FC = 0.1 TT = 1.583e-07 TREF = 25 BV = 81
 
+RS = 8.919e-03 N = 1.101e+00 IS = 1.599e-12 
+EG = 1.202e+00 XTI = -2.206e-02 TRS = 2.055e-03 
+CJO = 5.199e-10 VJ = 2.792e+00 M = 1.000e+00 ) 
.ENDS 
